/**
 * file: test15.v
 * Modules array test
 */

module cucu;
/*
 wire out;
 reg in_1, in_2;

 and2 ands [2:0] (in_1, in_2, out);
*/
 wire [1:0] out8;
 reg [1:0] in8_1, in8_2;

 and2 ands8 [1:0] (in8_1, in8_2, out8);

 initial begin
/*
   $write ("ands[0].aout\t | ands[1].aout\t | ands[2].aout\t | out\n");
   $write ("------------------------------------------------------\n");
   $strobe("%b \t\t | %b \t\t\t\t | %b \t\t | %b",
            ands[0].aout, ands[1].aout, ands[2].aout, out);
   in1 = 0;
   in2 = 0;
   #1;
   in1 = 1;
   in2 = 1;
   #1;
*/
   $write ("\n\nands8[0].aout\t | ands8[1].aout\t | out8\n");
   $write ("------------------------------------------------------\n");
   $strobe("%b \t\t | %b \t\t\t | %b",
            ands8[0].aout, ands8[1].aout,  out8);
   in8_1 = 0;
   in8_2 = 0;
   #1;
   $strobe("%b \t\t | %b \t\t\t | %b",
            ands8[0].aout, ands8[1].aout,  out8);   
   in8_1 = 8'b11;
   in8_2 = 8'b01;
   #2;
 end

endmodule

module and2(ain1, ain2, aout);
 input ain1, ain2;
 output aout;
 wire ain1, ain2, aout = ain1 & ain2;
/* initial begin
   $strobe("%m.aout = %b", aout);
   $display("this: %m");
 end*/
endmodule


